The Third Decade The FPGA as SoC — Volkswagen Constellation

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The Third Decade: The FPGA as SoC

By Ron Editor-in-Chief, Altera Corporation

In amidst the recessionary hangover the dot-com crash, Altera its third decade. It was a year of the tragic loss of the space Columbia, the last contact the spacecraft Pioneer 10, the last VW from the assembly line. And it was a of beginnings: the Iraq War, the of the great bull market in stocks, the first trans-sonic of the privately-developed SpaceShipOne, the first spaceflight by China.

This enabled an entirely new way of thinking programmable logic. Designers continue to build glue in CPLDs. Seekers of high would continue to implement ever more powerful and subsystems in packet-switching, signal-processing, and applications. But in addition, Altera’s decade would be the dawn of the as system on chip.

The CPU-Centric

Early in the decade, SoCs to follow a simple pattern, on the board-level computers they replacing. An SoC typically comprised a CPU core, a local cache or SRAM, a DRAM controller, an version of a microprocessor bus, and peripheral controllers the application (Figure 1 ). Applications might in this picture a DMA controller or an accelerator for some frequent but task, such as data cryptographic computations, or Fast Transforms (FFTs).

Figure 1. A CPU-Centric Soc Design

Implementing the SoC in an offered some valuable Designer could select the hardware blocks they in the CPU core. Numerical accelerators use the fast digital signal (DSP) blocks in Altera to achieve arithmetic performance beyond what the combination of a and a DSP chip could reach. And a could implement custom using the programmable logic, DSP and RAM blocks embedded in the FPGA These accelerators could be either as units on the microprocessor bus or as flow-through processors, creating a plane separate from the control plane.

An important advantage of this integration, according to Altera planning manager Bernhard was energy efficiency. Hard such as RAM and DSP blocks in the FPGA at least as energy-efficient as an equivalent or off-the-shelf function. Functions in the programmable logic would not always—consume more power their standard-product equivalents. But this period I/O dominated consumption in many systems. And data through the FPGA was not only vastly faster, but far efficient than moving it chip boundaries. By confining data transfers inside the system designers could achieve very substantial net savings at the system level.

the hardware and IP to support CPU-centric already in place, Altera on the tool flow. It was quickly that the tool needs of SoC were different from of traditional logic designers. designers of interfaces or datapath would express every of their design in VHDL or and then follow each through the steps of logic mapping to the FPGA resources, and closure.

But SoC designers focused at a abstract level. Was the hardware enough and the on-chip RAM large Were the bus and memory bandwidths Did the bus interfaces interoperate? With IP reuse, the focus of design shifted from the overall SoC to writing software, and to creating one or two new to drop into a design from existing IP. In other SoC developers were thinking system designers, not like designers.

One result of this shift in was Incremental Compilation, first by Altera in 2005. Often, effort would focus on one or two in an SoC, while the majority of the work remained unchanged. Incremental Compilation feature designers to rework one portion of a subject to fixed location and pin without having to run the entire back through the tool It not only saved compilation but it removed the risk of disturbing the of the hardware that was already

SoC designs also introduced a in the use of FPGA I/O pins. As bus bridges or FPGA s tended to have flowing through the chip in or streams, usually from one bus into another. Typically would be only a few clock mostly defined by the busses.

SoCs presented new requirements. would often be a standard bus, such as PCI or USB. But now the would be the originator of the bus, not a client on the bus. There also, almost certainly, be a port, drawing FPGAs the challenging trajectory of DDR SDRAM technology. And there would be a number of serial or parallel between on-chip peripheral and their external devices. diversity could mean pins, more signaling and variety in the I/O, and more domains. These changes reflected in increasing complexity of I/O cells and clock networks.

and Multicore

The treadmill of semiconductor improvements continued to run, out ever higher transistor But during Altera’s third the mill became less and able to produce higher speeds. Accordingly, CPU manufacturers from ever-higher core frequencies to two—and then and then more—CPU cores on one multicore architectures. SoC designers followed, both in ASIC and in FPGAs.

Multicore thinking had two significant in FPGA use. One thread replicated CPU cores. By this it was relatively easy to compile processor cores into one It was less simple, though, to out how to connect them. Here, logic offered an embarrassment of as architects could implement anything from arrays of cores to shared L2 cache to independent CPUs on the multimaster ® bus.

The second line of thinking led down a different heterogeneous systems. The same IP, and tools that made instances of one CPU core feasible combinations of a CPU core and multiple, accelerators just as possible 2 ). And this, in turn, led to an entirely way of thinking about multicore a software-centric approach.

Figure 2. A Multicore SoC Design

Planning a multicore system can be—to oversimplify—pretty straightforward. Figure out how times faster than speed you need to go. Put in that more CPUs, and maybe an or two to account for inefficiencies. Choose an architecture based on the level of sharing between threads you expect. Divide up your threads among the CPUs, the system, and repeat until it within specs. This remains firmly hardware-centric, an architecture, implementing it, and then up the code to fit the hardware.

But the ability to your own accelerators opens up a new methodology. It goes like Profile your code to the hot spots. For the nastiest code create custom accelerators will save both CPU and energy. Simulate the system, and to the profiling step and repeat, the performance requirements are met. approach starts with software on one CPU core, and generates a of hardware accelerators customized to the system software. For the first the system becomes a reflection of the requirements, rather than a bed into which the software be condemned.

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In 2006, Altera introduced two that supported this multicore design style. One was a that would transform a of executable ANSI C code an accelerator optimized to work a Nios ® CPU core in an Altera This C-to-Hardware Acceleration compiler tool automated one of the time-consuming and error-prone steps in design: generation of the accelerators.

The innovation was less obvious. If you the power consumption of a fast processor to that of an equivalent of slower-clocked processors, dynamic should go down sharply of the efficiencies of the accelerators. But leakage—a problem throughout the decade—increases the total number of transistors, of circuit activity. So leakage could take away of the energy efficiency that design provided.

Altera to this problem with a innovation: Programmable Power. combination of hardware and software-tool selects slower, low-leakage for non-critical timing paths, leakage current in the FPGA delivering timing closure. The could be recapturing the big energy that heterogeneous multicore had to offer, despite the higher of deep-submicron processes.

Consensus and

A final phase marked the years of Altera’s third the growth of consensus on IP selection. the system design community is its focus on specific solutions to of its most pressing problems. In C has become nearly ubiquitous embedded-system developers, ARM ® cores are to dominate embedded computing, and a few interface standards are coming to specific uses, such as system busses, backplane and inter-chip connections. That is allowing Altera to innovate in its of these solutions.

One example is in the way express parallelizeable chunks of C, while it is sufficient to define a procedure to implement a task, express the opportunities for parallelism a skilled programmer can find. But a called OpenCL™ can. In Altera introduced a set of tools allowed programmers to write algorithms in the increasingly popular and translate them—without specialized of FPGA design—into parallel in the FPGA and control code on a CPU.

The growing consensus the use of ARM Cortex™-A-class CPU cores in multicore enabled a second innovation. As as every design team a different CPU, FPGA had to meet these needs soft cores implemented in the logic. But that flexibility had its logic-element consumption, power and lower speed.

Altera to a specific trend: the use of the Cortex-A9 in a number of embedded and wireless In 2012, the company began an FPGA with an on-die Processor Subsystem: a dual-core cluster with its own caches, RAM, optimized memory and selected peripheral controllers, all in cell-based hardware. The chip took particular care to the interconnect between the subsystem and the logic fabric for implementing multicore systems.

This increasing convergence multicore processor systems and led to one more major innovation. In Altera announced that its generation of high-end FPGAs be fabricated not by a traditional foundry but by Intel Corp. using a 14 nm process whose heritage was own CPUs and SoCs. This from the ASIC-oriented foundry to the foundry arm of a CPU specialist in effect put FPGAs on a separate power-performance optimizing the semiconductor process that are vital to processing local RAM, and high-speed rather than optimizing the much wider space a broad-market ASIC foundry serve.

Altera believes the result of this choice be a discontinuity in the performance and energy patterns that have the FPGA industry for years. It is a way to start a new decade.

Please that any information or views in our bylined articles are views of the endorsed nor supported by Altera Please feel free to us with your ideas, or article proposals. Just an e-mail to editor@altera.com .

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